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vishay siliconix dg441b, dg442b document number: 72625 s11-1350-rev. b, 04-jul-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 improved quad spst cmos analog switches description the dg441b, dg442b are mono lithic quad analog switches designed to provide high speed, low error switching of analog and audio signals. the dg44 1b, dg442b are upgrades to the original dg441, dg442. combing low on-resistance (45 ? , typ.) with high speed (t on 120 ns, typ.), the dg 441b, dg442b are ideally suited for data acquisition, communication systems, automatic test equipment, or medical instrumentation. charge injection has been minimized on the drain for use in sample-and-hold circuits. the dg441b, dg442b are built using vishay siliconix?s high-voltage silicon-gate proce ss. an epitaxial layer prevents latchup. when on, each switch conducts equally well in both directions and blocks input vo ltages to the supply levels when off. features ? halogen-free according to iec 61249-2-21 definition ? low on-resistance: 45 ? ? low power consumption: 1 mw ? fast switching action - t on : 120 ns ? low charge injection - q: - 1 pc ? ttl/cmos-compatible logic ? single supply capability ? compliant to rohs directive 2002/95/ec benefits ? less signal errors and distortion ? reduced power supply requirements ? faster throughput ? reduced pedestal errors ? simple interfacing applications ? audio switching ? data acquisition ? sample-and-hold circuits ? communication systems ? automatic test equipment ? medical instruments functional block diagram and pin configuration logic "0" ?? 0.8 v logic "1" ?? 2.4 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 s 1 s 2 v- v+ gnd nc s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic dg441b top view s 2 v+ nc s 3 in 3 d 3 d 4 in 4 in 2 d 2 d 1 in 1 s 1 v- gnd s 4 1 2 3 4 5 6 8 7 16 15 14 13 12 11 10 9 dg441b qfn16 (4 x 4 mm) truth table logic dg441b dg442b 0 on off 1offon ordering information temp range package part number - 40 c to 85 c 16-pin plastic dip dg441bdj dg441bdj-e3 dg442bdj dg442bdj-e3 16-pin narrow soic dg441bdy-e3 dg441bdy-t1-e3 dg442bdy-e3 dg442bdy-t1-e3 16 pin qfn 4 x 4 mm DG441BDN-T1-E4 dg442bdn-t1-e4
www.vishay.com 2 document number: 72625 s11-1350-rev. b, 04-jul-11 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes . limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/c above 75 c. d. derate 12 mw/c above 75 c. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit v+ to v- 44 v gnd to v- 25 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 or 30 ma, whichever occurs first continuous current (any terminal) 30 ma current, s or d (pulsed at 1 ms, 10 % duty cycle ) 100 storage temperature - 65 to 125 c power dissipation (package) b 16-pin plastic dip c 470 mw 16-pin narrow body soic d 900 qfn-16 d 850
document number: 72625 s11-1350-rev. b, 04-jul-11 www.vishay.com 3 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 specifications a (for dual supplies) parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v e temp. b limits - 40 c to 85 c unit min. d typ. c max. d analog switch analog signal range e v analog full - 15 15 v drain-source on-resistance r ds(on) i s = 1 ma, v d = 10 v room full 45 80 95 ? on-resistance match between channels e ? r ds(on) i s = 1 ma, v d = 10 v room full 2 4 5 switch off leakage current i s(off) v d = 14 v, v s = 14 v room full - 0.5 - 5 0.01 0.5 5 na i d(off) room full - 0.5 - 5 0.01 0.5 5 channel on leakage current i d(on) v s = v d = 14 v room full - 0.5 - 10 0.02 0.5 10 digital control input voltage low v inl full 0.8 v input voltage high v inh full 2.4 input current v in low i inl v in under test = 0.8 v all other = 2.4 v full - 1 - 0.01 1 a input current v in high i inh v in under test = 2.4 v all other = 0.8 v full - 1 0.01 1 dynamic characteristics tu r n - o n t i m e t on r l = 1 k ? , c l = 35 pf v s = 10 v, see figure 2 room 120 220 ns turn-off time t off room 65 120 charge injection e q c l = 1 nf, v s = 0 v v gen = 0 v, r gen = 0 ? room - 1 pc off isolation e oirr r l = 50 ? , c l = 15 pf v s = 1 v rms , f = 100 khz room - 90 db crosstalk (channel-to-channel) x ta l k room - 95 sourceoff capacitance e c s(off) f = 1 mhz room 4 pf drain off capacitance e c d(off) room 4 channel on capacitance e c d(on) v s = v d = 0 v, f = 1 mhz room 16 power supplies positive supply current i+ v+ = 16.5 v, v- = - 16.5 v v in = 0 or 5 v room full 1 5 a negative supply current i- room full - 1 - 5
www.vishay.com 4 document number: 72625 s11-1350-rev. b, 04-jul-11 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. refer to process option flowchart. b. room = 25 c, full = as determin ed by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. schematic diagram (typical channel) specifications (for single supply) parameter symbol test conditions unless otherwise specified v+ = 12 v, v- = 0 v v in = 2.4 v, 0.8 v e temp. b limits - 40 c to 85 c unit min. d typ. c max. d analog switch analog signal range e v analog full 0 12 v drain-source on-resistance r ds(on) i s = 1 ma, v d = 3 v, 8 v room full 90 160 200 ? dynamic characteristics tu r n - o n t i m e t on r l = 1 k ? , c l = 35 pf, v s = 8 v see figure 2 room 120 300 ns turn-off time t off room 60 200 charge injection q c l = 1 nf, v gen = 6 v, r gen = 0 ? room 4 pc power supplies positive supply current i+ v in = 0 v or 5 v room full 1 5 a negative supply current i- room full - 1 - 5 figure 1. in x 5 v reg level shift/ drive v+ gnd v- v- v+
document number: 72625 s11-1350-rev. b, 04-jul-11 www.vishay.com 5 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) r ds(on) vs. v d and power supply voltages r ds(on) vs. v d and single power supply voltages leakage currents vs. analog voltage - 20 - 16 - 12 - 8 - 4 0 4 8 12 16 20 40 50 60 70 80 90 100 11 0 r ds(on) ( ) 5 v v d ? drain voltage (v) 10 v 15 v 20 v 30 20 10 0246810121416 0 25 50 75 100 125 150 175 200 225 r ds(on) ( ) v d ? drain voltage (v) v+ = 5 v 7 v 10 v 12 v 15 v 250 i s( o f f ) , i d( of f) i d( on) - 20 - 15 - 10 5 0 5 10 15 20 80 60 40 20 0 - 20 - 40 - 60 - 80 temperature (c) i s, i d ? current (pa) v+ = 22 v t a = 25 c v- = - 22 v r ds(on) vs. v d and temperature input switching threshold vs. supply voltage leakage currents vs. temperature 0 10 20 30 40 50 - 15 - 10 - 5 0 5 1 0 1 5 r ds(on) ( ) v d drain voltage (v) 125 c 85 c 25 c - 55 c v+ = 15 v v- = - 15 v 60 70 80 90 100 0 0.5 1 1.5 2 2.5 v th (v) 4 6 8 1 01 21 4 1 61 8 2 0 v+ positive supply (v) i s , i d - current - 55 25 45 5 - 15 65 1 na 100 pa 10 pa - 35 1 pa 85 105 125 v+ = 15 v v- = - 15 v v s, v d = 14 v i s( o f f ) , i d( of f) temperature (c)
www.vishay.com 6 document number: 72625 s11-1350-rev. b, 04-jul-11 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) switching time vs. single supply voltage q s , q d - charge injection vs. analog voltage 0 2468 1 0 1 2 1 4 1 6 1 8 2 0 100 200 300 400 500 v - = 0 v t on t of f switching time (ns) v+ ? positive supply (v) - 15 - 10 - 5 0 5 1 0 30 20 10 0 - 10 - 20 - 30 v+ = 15 v v- = - 15 v v+ = 12 v v- = 0 v q ? charge (pc) v analog ? analog voltage (v) 15 switching times vs. power supply voltage off isolation vs. frequency 0 100 200 300 400 t on t of f switching time (ns) 0 4 8 12 16 20 v+, v? positive and negative supplies (v) v+ = 15 v v- = - 15 v r l = 50 oirr (db) f - frequency (hz) 10 k 100 k 1 m 10 m 120 110 100 90 80 70 60 50 40 uy urren cn frequency 1 k 10 k 100 k 1 m 4 3 2 1 0 i+ ? supply current (ma) f ? frequency (hz)
document number: 72625 s11-1350-rev. b, 04-jul-11 www.vishay.com 7 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 2. switching time 0 v logic input switch input switch output 3 v 50 % 0 v v o v s t r < 20 ns t f < 20 ns t off t on note: logic input waveform is inverted for dg442. 50 % 80 % 80 % 10 v c l (includes fixture and stray capacitance) v- v+ in s d 3 v r l 1 k c l 35 pf v o - 15 v gnd + 15 v figure 3. charge injection off on off off on off v o v o in x in x q = v o x c l (dg441b) (dg442b) c l 1 nf in d v o v- v+ s 3 v r g - 15 v gnd + 15 v figure 4. crosstalk c = 1 mf tantalum in parallel with 0.01 mf ceramic 50 d 1 v o r g = 50 s 1 + 15 v - 15 v d 2 gnd v+ v- nc c c s 2 r l in 1 x ta l k isolation = 20 log v s v o 0 v, 2.4 v 0 v, 2.4 v v s in 2 c = rf bypass figure 5. off isolation s in r l d r g = 50 v s v o 0 v, 2.4 v off isolation = 20 log v s v o v+ - 15 v gnd v- c c + 15 v figure 6. source/drain capacitances s d in + 15 v - 15 v gnd v+ v- c c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent
www.vishay.com 8 document number: 72625 s11-1350-rev. b, 04-jul-11 vishay siliconix dg441b, dg442b this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 applications vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a com posite of all qualified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see www.vishay.com/ppg?72625 . figure 7. power mosfet driver + 15 v + 15 v gnd v- v+ 0 = load off 1 = load on + 24 v i = 3a vn0300 l, m dg442b + 15 v 10 k 150 r l in figure 8. open loop sample-and-hold h = sample l = hold - 15 v + 15 v v in v out c h sd in 1/4 dg442b + - + - figure 9. precision-weighted resistor programmable-gain amplifier + 15 v - 15 v v+ v- gnd dg441 or dg442 + - v in v out gain error is determined only by the resistor tolerance. op amp offset and cmrr will limit ac- curacy of circuit. gain 1 a v = 1 gain 2 a v = 10 gain 3 a v = 20 gain 4 a v = 100 r 1 90 k r 2 5 k r 3 4 k r 4 1 k v out v in = r 1 + r 2 + r 3 + r 4 r 4 = 100 with sw 4 closed
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 12345678 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71261 06-jul-01 www.vishay.com 1

dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 18.93 21.33 0.745 0.840 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.38 1.52 .015 0.060 ecn: s-03946?rev. d, 09-jul-01 dwg: 5482
terminal tip 5 index area (d 2 e 2) exposed pad 8 -b- d d/2 e/2 -a- e c aaa 2 x top view aa1 a3 -c- seating plane side view bb dd aa cc detail a c 0.08 nx 9 c ccc // d2 d2/2 detail b (ne-1) x e 6 n l e2/2 e2 detail a 2 1 n-1 n (nd-1) x e 8 bottom view c bbb m a b n b 5 datum a or b n r e terminal tip 5 even terminal/side odd terminal/side detail b e e/2 4 c aaa 2 x package information vishay siliconix document number: 71921 19-aug-02 www.vishay.com 1 qfn?16 (4 4 mm) jedec part number: mo-220
notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. all angels are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 iden tifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a molded or marked feature. the x and y dimens ion will vary according to lead counts. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. 6. nd and ne refer to the number of terminals on the d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. variation hhd is shown for illustration only. 9. coplanarity applies to the exposed heat sink slug as well as the terminals. package information vishay siliconix www.vishay.com 2 document number: 71921 19-aug-02 qfn?16 (4 4 mm) jedec part number: mo-220 millimeters* inches dim min nom max min nom max notes a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0 0.02 0.05 0 0.0008 0.0020 a3 - 0.20 ref - - 0.0079 - aa - 0.345 - - 0.0136 - aaa - 0.25 - - 0.0098 - bb - 0.345 - - 0.0136 - b 0.23 0.30 0.38 0.0091 0.0118 0.0150 5 bbb - 0.10 - - 0.0039 - cc - 0.18 - - 0.0071 - ccc - 0.10 - - 0.0039 - d 4.00 bsc 0.1575 bsc d2 2.00 2.15 2.25 0.0787 0.0846 0.0886 dd - 0.18 - - 0.0071 - e 4.00 bsc 0.1575 bsc e2 2.00 2.15 2.25 0.0787 0.0846 0.0886 e 0.65 bsc 0.0256 bsc l 0.45 0.55 0.65 0.0177 0.0217 0.0256 n 16 16 3, 7 nd - 4 - - 4 - 6 ne - 4 - - 4 - 6 r b(min)/2 - - b(min)/2 - - * use millimeters as the primary measurement. ecn: s-21437?rev. a, 19-aug-02 dwg: 5890
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
vishay siliconix an505 document number: 74976 19-apr-07 www.vishay.com 1 recommended minimum pads for qfn-16 (4 x 4 mm body) note: qfn-16 (4 x 4) has an exposed center pad that must not come into contact with any metalized structure on the pcb. this area is considered a keep out zone. inches millimeters c1 0.142 3.60 c2 0.142 3.60 e 0.026 0.65 x1 0.014 0.35 x2 0.089 2.25 y1 0.037 0.95 y2 0.089 2.25 1 2 3 4 12 11 10 9 16 15 14 1 3 5 6 7 8 keep o u t zone c1 x2 x1 e y1 c2 y2
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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